The present invention relates to integrated circuits, and in particular to a delay locked loop in a memory device.
Delay locked loops (DLLs) are often used in integrated circuits (ICs) to generate an internal clock signal. In a typical DLL, the internal clock signal is generated by applying an amount of delay to a system clock or an external clock signal. The DLL tracks the external and internal clock signals with a detect operation and adjusts the amount of delay with a shifting operation to keep the internal and external clock signals synchronized.
In some integrated circuit devices, such as dynamic random access memory (DRAM) devices, the internal clock signal generated by the DLL is normally used as a timing signal for certain operations of the memory device. For example, in some memory devices, the internal clock signal can be used as a clock signal to provide timing for data transfer to and from the memory device.
A traditional memory device has a number of memory cells for storing data. To store data into the memory cells, a WRITE operation is performed. To retrieve the stored data, a READ operation is performed. Typically, a WRITE or READ operation includes two separate modes, an ACTIVE mode followed by a WRITE or READ mode. In the ACTIVE mode, the memory device activates a so-called ACTIVE command signal to xe2x80x9copenxe2x80x9d or activate the memory cells in preparation for a subsequent WRITE or READ mode. Following the ACTIVE mode, if it is a READ operation, the memory device activates a so-called READ command signal to access the activated memory cells to read the stored data in the memory cells.
Typically, activating the memory cells during the ACTIVE mode or accessing the memory cells during the READ mode demands a higher than normal amount of current which causes the internal supply voltage of the memory device to drop. The drop in the internal supply voltage changes the voltage supplied to the DLL. The change in the voltage supplied to the DLL causes a change in the amount of delay applied to the external clock signal. The change in the amount of delay causes the external and internal clock signals to be out of synchronism. When the external and internal signals are out of synchronism, the DLL performs a shifting operation to adjust the amount of delay to compensate for the drop in voltage during the ACTIVE mode to eventually put the external and internal clock signals back to synchronism.
Although the external and internal clock signals are eventually synchronized after the ACTIVE mode, the shifting operation during the ACTIVE mode may put the DLL in an unknown condition, which may change the timing for the data transfer of the memory device and move the data output timing out of the specification requirement. This change in the timing may not provide satisfactory level of accuracy for the data transfer of the memory device especially for new generations of high speed memory devices.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need for a method to control a DLL in an integrated circuit device such as a memory device during an ACTIVE or memory operational mode such as the ACTIVE or READ mode.
The present invention includes a method for controlling the DLL during a memory operational mode by disabling a synchronization operation of the DLL during the memory operational mode, such as an ACTIVE mode or a READ mode, so that the so that an unknown shifting condition of the DLL can be avoided to reduce the effect of a change in operating condition of the memory device to the DLL during the operational mode.
In one aspect, a memory device is provided. The memory device includes a DLL for generating an internal clock signal based on an external clock signal. The DLL keeps the external and internal clock signals synchronized by performing a synchronization operation. The memory device further includes a DLL controller connected to the DLL. During an operational mode of the memory device such as ACTIVE, READ or REFRESH mode, the DLL controller activates a DLL control signal to prevent the DLL from performing the synchronization operation.
In another aspect, a method of operating a DLL in a memory device is provided. The method includes generating an internal clock signal based on an external clock signal. The method also includes performing a synchronization operation to keep the external and internal clock signals synchronized. The method further includes activating a DLL control signal to disable the synchronization operation of the DLL during an operational of the memory device.